m5stack_core/board/
display.rs

1// SPDX-License-Identifier: MIT OR Apache-2.0
2//! ILI9342C panel bring-up shared by both boards (feature `display`).
3//!
4//! The M5Stack Fire27 and CoreS3 use the same 320x240 ILI9342C panel with the
5//! same controller options (inverted colors, BGR order); only the reset wiring
6//! differs — Fire27 has a GPIO reset pin, the CoreS3 panel is reset via the
7//! AW9523B expander (see [`super::cores3::power_display_reset`]) and
8//! falls back to lcd-async's SPI `SoftReset` ([`NoResetPin`]), which is
9//! harmless after the hardware pulse.
10//!
11//! Generic over the [`Interface`]: works with a plain shared `Spi` bus device
12//! (the examples) as well as a descriptor-backed `SpiDmaBus` device
13//! ([`super::spi2`]).
14
15use core::convert::Infallible;
16
17use embedded_hal::digital::OutputPin;
18use lcd_async::{
19    Builder, Display, InitError, NoResetPin,
20    interface::Interface,
21    models::ILI9342CRgb565,
22    options::{ColorInversion, ColorOrder},
23};
24
25/// Panel resolution — the single per-target source in [`super`] (a board fact,
26/// not display-driver-specific); re-exported here for the display API.
27pub use super::{SCREEN_H, SCREEN_W};
28
29/// The configured panel type: ILI9342C in RGB565 over `DI`.
30pub type Ili9342c<DI, RST = NoResetPin> = Display<DI, ILI9342CRgb565, RST>;
31
32fn builder<DI: Interface>(di: DI) -> Builder<DI, ILI9342CRgb565, NoResetPin> {
33    Builder::new(ILI9342CRgb565, di)
34        .invert_colors(ColorInversion::Inverted)
35        .color_order(ColorOrder::Bgr)
36        .display_size(SCREEN_W, SCREEN_H)
37}
38
39/// Initialise the panel without a reset pin (CoreS3). The hardware reset must
40/// have been pulsed beforehand (AW9523B `LCD_RST`); init falls back to a SPI
41/// `SoftReset` command.
42pub async fn init_ili9342c<DI: Interface>(
43    di: DI,
44) -> Result<Ili9342c<DI>, InitError<DI::Error, Infallible>> {
45    let mut delay = embassy_time::Delay;
46    builder(di).init(&mut delay).await
47}
48
49/// Initialise the panel with a hardware reset pin (Fire27, RST=GPIO33).
50pub async fn init_ili9342c_with_reset<DI: Interface, RST: OutputPin>(
51    di: DI,
52    rst: RST,
53) -> Result<Ili9342c<DI, RST>, InitError<DI::Error, RST::Error>> {
54    let mut delay = embassy_time::Delay;
55    builder(di).reset_pin(rst).init(&mut delay).await
56}
m5stack_core/board/display.rs

m5stack_core/board/
display.rs
